Digital Electronics - Flip-Flops
Exercise : Flip-Flops - General Questions
- Flip-Flops - General Questions
- Flip-Flops - True or False
- Flip-Flops - Filling the Blanks
56.
As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:
57.
A positive edge-triggered D flip-flop will store a 1 when ________.
58.
If an input is activated by a signal transition, it is ________.
59.
A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What causes the glitches, and how might the problem be corrected?
60.
A 555 operating as a monostable multivibrator has a C1 = 100
F. Determine R1 for a pulse width of 500 ms.

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