# Digital Electronics - Flip-Flops

Exercise : Flip-Flops - General Questions
1.
Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
10.24 kHz
5 kHz
30.24 kHz
15 kHz
Explanation:
No answer description is available. Let's discuss.

2.
Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?
The logic level at the D input is transferred to Q on NGT of CLK.
The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
The Q output is ALWAYS identical to the D input when CLK = PGT.
The Q output is ALWAYS identical to the D input.
Explanation:
No answer description is available. Let's discuss.

3.
Propagation delay time, tPLH, is measured from the ________.
triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
preset input to the LOW-to-HIGH transition of the output
clear input to the HIGH-to-LOW transition of the output
Explanation:
No answer description is available. Let's discuss.

4.
How is a J-K flip-flop made to toggle?
J = 0, K = 0
J = 1, K = 0
J = 0, K = 1
J = 1, K = 1