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Digital Electronics - Flip-Flops

Why Digital Electronics Flip-Flops?

In this section you can learn and practice Digital Electronics Questions based on "Flip-Flops" and improve your skills in order to face the interview, competitive examination and various entrance test (CAT, GATE, GRE, MAT, Bank Exam, Railway Exam etc.) with full confidence.

Where can I get Digital Electronics Flip-Flops questions and answers with explanation?

IndiaBIX provides you lots of fully solved Digital Electronics (Flip-Flops) questions and answers with Explanation. Solved examples with detailed answer description, explanation are given and it would be easy to understand. All students, freshers can download Digital Electronics Flip-Flops quiz questions with answers as PDF files and eBooks.

Where can I get Digital Electronics Flip-Flops Interview Questions and Answers (objective type, multiple choice)?

Here you can find objective type Digital Electronics Flip-Flops questions and answers for interview and entrance examination. Multiple choice and true or false type questions are also provided.

How to solve Digital Electronics Flip-Flops problems?

You can easily solve all kind of Digital Electronics questions based on Flip-Flops by practicing the objective type exercises given below, also get shortcut methods to solve Digital Electronics Flip-Flops problems.

Home » Engineering » Digital Electronics » Flip-Flops » General Questions

Exercise :: Flip-Flops - General Questions

1. 

Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
A. 10.24 kHz
B. 5 kHz
C. 30.24 kHz
D. 15 kHz

Answer: Option B

Explanation:

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2. 

Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?
A. The logic level at the D input is transferred to Q on NGT of CLK.
B. The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
C. The Q output is ALWAYS identical to the D input when CLK = PGT.
D. The Q output is ALWAYS identical to the D input.

Answer: Option A

Explanation:

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3. 

Propagation delay time, tPLH, is measured from the ________.
A. triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
B. triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
C. preset input to the LOW-to-HIGH transition of the output
D. clear input to the HIGH-to-LOW transition of the output

Answer: Option A

Explanation:

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4. 

How is a J-K flip-flop made to toggle?
A. J = 0, K = 0
B. J = 1, K = 0
C. J = 0, K = 1
D. J = 1, K = 1

Answer: Option D

Explanation:

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5. 

How many flip-flops are in the 7475 IC?
A. 1
B. 2
C. 4
D. 8

Answer: Option C

Explanation:

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6. 

How many flip-flops are required to produce a divide-by-128 device?
A. 1
B. 4
C. 6
D. 7

Answer: Option D

Explanation:

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