Digital Electronics - Flip-Flops

Exercise :: Flip-Flops - Filling the Blanks

1. 

The asynchronous inputs are normally labeled ________ and ________, and are normally active-________ inputs.

A. PRE, CLR, LOW
B. ON, OFF, HIGH
C. START, STOP, LOW
D. SET, RESET, HIGH

Answer: Option A

Explanation:

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2. 

Assume a J-K flip-flop has 1s on the J and K inputs. The next clock pulse will cause the output to ________.

A. set
B. reset
C. latch
D. toggle

Answer: Option D

Explanation:

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3. 

In synchronous systems, the exact times at which any output can change state are determined by a signal commonly called the ________.

A. traffic
B. D
C. flip-flop
D. clock

Answer: Option D

Explanation:

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4. 

The key to edge-triggered sequential circuits in VHDL is the ________.

A. ARCHITECTURE
B. PROCESS
C. FUNCTION
D. VARIABLE

Answer: Option B

Explanation:

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5. 

Assume an latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ________.

A.
B.
C.
D.

Answer: Option D

Explanation:

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