Digital Electronics - Flip-Flops
Exercise : Flip-Flops - Filling the Blanks
- Flip-Flops - General Questions
- Flip-Flops - True or False
- Flip-Flops - Filling the Blanks
1.
The asynchronous inputs are normally labeled ________ and ________, and are normally active-________ inputs.
2.
Assume a J-K flip-flop has 1s on the J and K inputs. The next clock pulse will cause the output to ________.
3.
In synchronous systems, the exact times at which any output can change state are determined by a signal commonly called the ________.
4.
The key to edge-triggered sequential circuits in VHDL is the ________.
5.
Assume an 
latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ________.
latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ________.
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