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Digital Electronics - Flip-Flops

Exercise : Flip-Flops - Filling the Blanks
6.
The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as a ________.
FUNCTION
logic primitive
VARIABLE
PROCESS
Answer: Option
Explanation:
No answer description is available. Let's discuss.
7.
A gated D latch does not have ________.
a clock input
an enable input
a output
steering gates
Answer: Option
Explanation:
No answer description is available. Let's discuss.
8.
Setup time specifies ________.
the minimum time for the control levels to be maintained on the inputs prior to the triggering edge of the clock in order for data to be reliably clocked into the FF
the maximum time interval required for the control levels to remain on the inputs before the triggering edge of the clock in order for the data to be reliably clocked out of the FF
how long the operator has in order to get the flip-flop running before the maximum power level is exceeded
how long it takes the output to change states after the clock has transitioned
Answer: Option
Explanation:
No answer description is available. Let's discuss.
9.
When the output of the NOR gate S-R flip-flop is Q = 0 and , the inputs are:
S = 1, R = 1
S = 1, R = 0
S = 0, R = 1
S = 0, R = 0
Answer: Option
Explanation:
No answer description is available. Let's discuss.
10.
A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ mS.
3
7
10
13
Answer: Option
Explanation:
No answer description is available. Let's discuss.
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