Digital Electronics - Flip-Flops

Exercise :: Flip-Flops - True or False

1. 

A gated S-R flip-flop goes into the SET condition when S is HIGH, R is LOW, and EN is HIGH.

A. True
B. False

Answer: Option A

Explanation:

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2. 

VHDL does require a special designation for an output with a feedback.

A. True
B. False

Answer: Option A

Explanation:

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3. 

A negative edge-triggered flip-flop will accept inputs only when the clock is LOW.

A. True
B. False

Answer: Option B

Explanation:

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4. 

The term CLEAR always means that .

A. True
B. False

Answer: Option A

Explanation:

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5. 

PRESET and CLEAR inputs are normally synchronous.

A. True
B. False

Answer: Option B

Explanation:

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