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Digital Electronics - Flip-Flops

Exercise : Flip-Flops - General Questions
51.
Which of the following best describes the action of pulse-triggered FF's?
The clock and the S-R inputs must be pulse shaped.
The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.
A pulse on the clock transfers data from input to output.
The synchronous inputs must be pulsed.
Answer: Option
Explanation:
No answer description is available. Let's discuss.
52.
An invalid condition in the operation of an active-HIGH input S-R latch occurs when ________.
HIGHs are applied simultaneously to both inputs S and R
LOWs are applied simultaneously to both inputs S and R
a LOW is applied to the S input while a HIGH is applied to the R input
a HIGH is applied to the S input while a LOW is applied to the R input
Answer: Option
Explanation:
No answer description is available. Let's discuss.
53.
On a J-K flip-flop, when is the flip-flop in a hold condition?
J = 0, K = 0
J = 1, K = 0
J = 0, K = 1
J = 1, K = 1
Answer: Option
Explanation:
No answer description is available. Let's discuss.
54.
The output pulse width for a 555 monostable circuit with R1 = 3.3 k and C1 = 0.02 F is ________.
7.3 s
73 s
7.3 ms
73 ms
Answer: Option
Explanation:
No answer description is available. Let's discuss.
55.
Edge-triggered flip-flops must have:
very fast response times.
at least two inputs to handle rising and falling edges.
a pulse transition detector.
active-LOW inputs and complemented outputs.
Answer: Option
Explanation:
No answer description is available. Let's discuss.
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