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Electronics and Communication Engineering - Digital Electronics

Exercise : Digital Electronics - Section 9
1.

Assertion (A): In a parallel in-serial out shift register data is loaded one bit-at a time

Reason (R): A serial in-serial out shift register can be used to introduce a time delay.

Both A and R are correct and R is correct explanation of A
Both A and R are correct but R is not correct explanation of A
A is true, R is false
A is false, R is true
Answer: Option
Explanation:
No answer description is available. Let's discuss.
2.
In an 8085 microprocessor, the instruction CMP B has been executed while the content of the accumulator is less than that of register B, As a result.
carry flag will be set but zero flag will be reset
carry flag will be reset but zero flag will be set
both carry flag and zero flag will be reset
both carry flag and zero flag will be set
Answer: Option
Explanation:
No answer description is available. Let's discuss.
3.
Computers use thousands of flip-flops. To coordinate the overall action, a common signal is sent to all flip-flop known as
debug signal
toggle signal
active signal
clock signal
Answer: Option
Explanation:
No answer description is available. Let's discuss.
4.
In a D-type latch EN = 1, D = 1, the O/P is
1
0
don't care
blocked
Answer: Option
Explanation:
No answer description is available. Let's discuss.
5.
Which has the highest power dissipation per gate?
ECL
TTL
CMOS
PMOS
Answer: Option
Explanation:
No answer description is available. Let's discuss.
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