Electronics and Communication Engineering - Digital Electronics
Exercise :: Digital Electronics - Section 9
| 1. |
Assertion (A): In a parallel in-serial out shift register data is loaded one bit-at a time Reason (R): A serial in-serial out shift register can be used to introduce a time delay. |
| A. |
Both A and R are correct and R is correct explanation of A | | B. |
Both A and R are correct but R is not correct explanation of A | | C. |
A is true, R is false | | D. |
A is false, R is true |
Answer: Option D
Explanation:
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| 2. |
In an 8085 microprocessor, the instruction CMP B has been executed while the content of the accumulator is less than that of register B, As a result. |
| A. |
carry flag will be set but zero flag will be reset | | B. |
carry flag will be reset but zero flag will be set | | C. |
both carry flag and zero flag will be reset | | D. |
both carry flag and zero flag will be set |
Answer: Option A
Explanation:
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| 3. |
Computers use thousands of flip-flops. To coordinate the overall action, a common signal is sent to all flip-flop known as |
| A. |
debug signal | | B. |
toggle signal | | C. |
active signal | | D. |
clock signal |
Answer: Option D
Explanation:
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| 4. |
In a D-type latch EN = 1, D = 1, the O/P is |
Answer: Option A
Explanation:
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| 5. |
Which has the highest power dissipation per gate? |
Answer: Option A
Explanation:
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