Electronics and Communication Engineering - Digital Electronics
Exercise :: Digital Electronics - Section 14
| 1. |
A voltage DAC is generally slower than current DAC |
| A. |
because of more accuracy | | B. |
because of higher resolution | | C. |
because of response time of op-amp current to voltage converter | | D. |
none of the above |
Answer: Option C
Explanation:
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| 2. |
The circuit realizes the function
 |
| A. |
(A + B) E + CD | | B. |
(A + B) (E + CD) | | C. |
(A + B) (E + C + D) | | D. |
(AB + E). CD |
Answer: Option A
Explanation:
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| 3. |
For a NAND SR latch of input is the normal resting state of inputs is |
| A. |
S = R = 1 | | B. |
S = 0, R = 1 | | C. |
S = 1, R = 0 | | D. |
S = R = 0 |
Answer: Option A
Explanation:
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| 4. |
A mod-2 counter followed by a mod 5 is same as |
| A. |
mod-7 counter | | B. |
A decade counter | | C. |
mod-3 counter | | D. |
none |
Answer: Option B
Explanation:
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| 5. |
The write cycle time of memory is 200 nsec. The maximum rate of data which can be stored is |
| A. |
200 words/sec | | B. |
5 x 103 words/sec | | C. |
5 x 106 word/sec | | D. |
5 x 109 words/sec |
Answer: Option C
Explanation:
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