Exercise :: Digital Electronics - Section 6
- Digital Electronics - Section 1
- Digital Electronics - Section 2
- Digital Electronics - Section 3
- Digital Electronics - Section 4
- Digital Electronics - Section 5
- Digital Electronics - Section 6
- Digital Electronics - Section 7
- Digital Electronics - Section 8
- Digital Electronics - Section 9
- Digital Electronics - Section 10
- Digital Electronics - Section 11
- Digital Electronics - Section 12
- Digital Electronics - Section 13
- Digital Electronics - Section 14
- Digital Electronics - Section 15
- Digital Electronics - Section 16
- Digital Electronics - Section 17
- Digital Electronics - Section 18
- Digital Electronics - Section 19
- Digital Electronics - Section 20
- Digital Electronics - Section 21
- Digital Electronics - Section 22
- Digital Electronics - Section 23
- Digital Electronics - Section 24
| 21. | Assertion (A): Master slave JK flip flop is commonly used in high speed synchronous circuitry Reason (R): Master slave JK flip flop uses two JK flip flops in cascade. |
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Answer: Option D Explanation: R-S, J-K flip-flop is not used very commonly. |
| 22. | Inputs A and B of the given figure are applied to a NAND gate. The output is LOW |
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Answer: Option C Explanation: NAND gate gives Low output if all inputs are High. For other combinations of inputs, output is High. |
| 23. | ECL is a saturating logic. |
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Answer: Option B Explanation: It is a non-saturating logic. Hence highest speed of operation. |
| 24. | For the NMOS gate in the given figure, F = |
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Answer: Option C Explanation: B + C are in parallel and A is in series with this parallel combination, Similarly D + E are in series. Then D, E are in parallel with A, B and C Y = A(B + C) + DE . |
| 25. | The resolution of 4 bit counting ADC is 0.5 volt, for an Analog input of 6.6 volts. The digital output of ADC will be |
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Answer: Option B Explanation: Digital output of ADC resolution = |
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