Digital Electronics - Flip-Flops
Exercise : Flip-Flops - General Questions
- Flip-Flops - General Questions
- Flip-Flops - True or False
- Flip-Flops - Filling the Blanks
66.
The output of a gated S-R flip-flop changes only if the:
67.
In VHDL, in which declaration section is a COMPONENT declared?
68.
A gated S-R latch and its associated waveforms are shown below. What, if anything, is wrong and what could be causing the problem?
The 
output is always low; the circuit is defective.
output is always low; the circuit is defective.The Q output should be the complement of the 
output; the S and R terminals are reversed.
output; the S and R terminals are reversed.The Q should be following the R input; the R input is defective.
There is nothing wrong with the circuit.
69.
The output pulse width of a 555 monostable circuit with R1 = 4.7 k
and C1 = 47 
F is ________.
and C1 = 47 F is ________.24 s
24 ms
243 ms
243 s
s70.
If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?
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