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Digital Electronics - Flip-Flops

Exercise : Flip-Flops - General Questions
71.

The circuit given below fails to function; the inputs are checked with a logic probe and the following indications are obtained: CLK, J1, J2, J3, K1, K2, and K3 are pulsing. Q and are HIGH. and PRE are LOW. What could be causing the problem?

There is no problem.
The clock should be held HIGH.
The PRE is stuck LOW.
The CLR is stuck HIGH.
Answer: Option
Explanation:
No answer description is available. Let's discuss.
72.
A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?
The power supply is probably noisy.
The switch contacts are bouncing.
The socket contacts on the register IC are corroded.
The register IC is intermittent and failure is imminent.
Answer: Option
Explanation:
No answer description is available. Let's discuss.
73.

A 555 timer is connected for astable operation as shown below along with the output waveform. It is determined that the duty cycle should be 0.5. What steps need to be taken to correct the duty cycle, while maintaining the same output frequency?

Increase the value of C.
Increase Vcc and decrease RL.
Decrease R1 and R2.
Decrease R1 and increase R2.
Answer: Option
Explanation:
No answer description is available. Let's discuss.
74.
The pulse width of a one-shot circuit is determined by ________.
a resistor and capacitor
two resistors
two capacitors
none of the above
Answer: Option
Explanation:
No answer description is available. Let's discuss.
75.
For an S-R flip-flop to be set or reset, the respective input must be:
installed with steering diodes
in parallel with a limiting resistor
LOW
HIGH
Answer: Option
Explanation:
No answer description is available. Let's discuss.
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