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Digital Electronics - Flip-Flops

Exercise : Flip-Flops - General Questions
21.
Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.
True
False
Answer: Option
Explanation:
No answer description is available. Let's discuss.
22.
Which of the following is correct for a D latch?
The output toggles if one of the inputs is held HIGH.
Q output follows the input D when the enable is HIGH.
Only one of the inputs can be HIGH at a time.
The output complement follows the input when enabled.
Answer: Option
Explanation:
No answer description is available. Let's discuss.
23.
A J-K flip-flop is in a "no change" condition when ________.
J = 1, K = 1
J = 1, K = 0
J = 0, K = 1
J = 0, K = 0
Answer: Option
Explanation:
No answer description is available. Let's discuss.
24.
A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:
clock is LOW
slave is transferring
flip-flop is reset
clock is HIGH
Answer: Option
Explanation:
No answer description is available. Let's discuss.
25.
Which of the following describes the operation of a positive edge-triggered D flip-flop?
If both inputs are HIGH, the output will toggle.
The output will follow the input on the leading edge of the clock.
When both inputs are LOW, an invalid state exists.
The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
Answer: Option
Explanation:
No answer description is available. Let's discuss.
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