Online Digital Electronics Test - Digital Electronics Test - Random

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Total number of questions: 20.
Time allotted: 30 minutes.
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Convert hexadecimal value 16 to decimal.

22₁₀

16₁₀

10₁₀

20₁₀

[#]

How many inputs are on the logic gates of a 74HC21 IC?

[#]

What is the Boolean expression for a four-input OR gate?

Y = A + B + C + D

Y = A· B · C · D

Y = A – B – C – D

Y = A $ B $ C $ D

[#]

Derive the Boolean expression for the logic circuit shown below:

[#]

Each "1" entry in a K-map square represents:

a HIGH for each input truth table condition that produces a HIGH output.

a HIGH output on the truth table for all LOW input combinations.

a LOW output for all possible HIGH input conditions.

a DON'T CARE condition for all possible input truth table combinations.

[#]

Which is not a real advantage of HDL?

Using higher levels of abstraction

Tailoring components to exactly fit the needs of the project

The use of graphical tools

Using higher levels of abstraction and tailoring components to exactly fit the needs of the project

[#]

ICs can perform sequential operations, including counting and data shifting.

True

False

[#]

A positive edge-triggered flip-flop changes states with a HIGH-to-LOW transition on the clock input.

True

False

[#]

Referring to the given figure, at which point is the serial data transferred to the parallel output?

[#]

10.

Most sequential circuits contain a combinational logic section and a memory section.

True

False

[#]

11.

How would a latch circuit be used in a microprocessor system?

as transportation for Intel employees

for a group of data that is the same

as a set of common connections for transfer of data

[#]

12.

CMOS is a more dominant IC technology than TTL.

True

False

[#]

13.

A half-adder circuit would normally be used each time a carry input is required in an adder circuit.

True

False

[#]

14.

Usually P-MOS and N-MOS circuits are identical with the exception of the voltage polarities.

True

False

[#]

15.

ECL gates are noted for their high frequency capability and small output voltage swing.

True

False

[#]

16.

The HIGH logic level for a standard TTL output must be at least ________.

2.4 V

2 V

0.8 V

5 V

[#]

17.

Flash A/D converters depend on an input clock pulse to perform each conversion.

True

False

[#]

18.

A typical fan-out for most TTL is 9.

True

False

[#]

19.

An astable 555 timer has the following number of stable states:

[#]

20.

MOV A, @ R1 will:

copy R1 to the accumulator

copy the accumulator to R1

copy the contents of memory whose address is in R1 to the accumulator

copy the accumulator to the contents of memory whose address is in R1

[#]

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Online Digital Electronics Test - Digital Electronics Test - Random

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