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Electronics and Communication Engineering - Digital Electronics

Exercise : Digital Electronics - Section 24
16.
39.1210 = __________ 10
10111.0001111
100011.0001111
100001.0001111
001111.0001111
Answer: Option
Explanation:
No answer description is available. Let's discuss.
17.
Which of the following is best suited for parity checking and parity generation?
AND, OR, NOT gates
XOR, Exclusive NOR gate
NAND gates
NOR gates
Answer: Option
Explanation:
No answer description is available. Let's discuss.
18.
In the circuit shown below, the outputs Y1 and Y2 for the given initial condition Y1 = Y2 = 1 and after four input pulses will be
Y1 = 1, Y2 = 0
Y1 = 0, Y2 = 0
Y1 = 0, Y2 = 1
Y1 = 1, Y2 = 1
Answer: Option
Explanation:
No answer description is available. Let's discuss.
19.
The op amp is used in
A/D converters
D/A converters
both (a) and (b)
shift registers
Answer: Option
Explanation:
No answer description is available. Let's discuss.
20.

Assertion (A): Power drain of CMOS increases with operating frequency

Reason (R): All unused CMOS inputs should be tied either to a fixed voltage level (0 or VDD) or to another input.

Both A and R are correct and R is correct explanation of A
Both A and R are correct but R is not correct explanation of A
A is true, R is false
A is false, R is true
Answer: Option
Explanation:
No answer description is available. Let's discuss.
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