Electronics and Communication Engineering - Digital Electronics

46. 

The basic circuit configuration for TTL resembles that of a

A. AND gate
B. NAND gate
C. NOR gate
D. OR gate

Answer: Option B

Explanation:

No answer description available for this question. Let us discuss.

47. 

Time delay of a TTL standard family is about

A. 180 ns
B. 50 ns
C. 18 ns
D. 3 ns

Answer: Option C

Explanation:

No answer description available for this question. Let us discuss.

48. 

Assertion (A): Boolean expressions can be easily simplified using Karnaugh map.

Reason (R): Karnaugh map can be drawn for minterms as well as max terms.

A. Both A and R are correct and R is correct explanation of A
B. Both A and R are correct but R is not correct explanation of A
C. A is true, R is false
D. A is false, R is true

Answer: Option B

Explanation:

No answer description available for this question. Let us discuss.

49. 

In a flip flop which input determines the state to which output will transistion?

A. Control input
B. Clock input
C. Both control and clock input
D. Either control or clock input

Answer: Option A

Explanation:

No answer description available for this question. Let us discuss.

50. 

In a synchronous counter all flip flops are clocked together.

A. True
B. False

Answer: Option A

Explanation:

No answer description available for this question. Let us discuss.

« Prev   1 2 3 4 5 6 7 8 9 10