Electronics and Communication Engineering - Digital Electronics

Data from a satellite is received in serial form (1 bit after another). If this data is coming at a 5 MHz rate and if the clock frequency is 5 MHz how long will it take to serially load a word in a 32-bit shift register?

Assuming accumulator contain A 64 and the carry is set (1). What will register A and (CY) contain after CMA?

The minimum number of 2 input NAND gates required to implement Boolean function A B C is A, B, C are available is

Single parity check is not reliable in case of

A 0 to 6 counter consist of 3 flip-flop and a combinational circuit of 2 input gates. The combinational circuit consist of