Electronics and Communication Engineering - Digital Electronics

11. 

In a shift register the data is loaded in one operation but shifted out one bit at a time, The shift register is

A. serial in-serial out
B. parallel in-serial out
C. serial in-parallel out
D. parallel in-parallel out

Answer: Option B

Explanation:

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12. 

In CCD

A. a small charge is deposited for logical 1
B. a small charge is deposited for both logical 1 and 0
C. a small charge is deposited for logical 0 and large charge for logical 1
D. none of the above

Answer: Option C

Explanation:

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13. 

The contents of the program counter after the call operation point to the first instruction on the

A. stack
B. subroutine
C. either of the above
D. none of the above

Answer: Option B

Explanation:

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14. 

Dual slope ADC uses an op amp comparator.

A. True
B. False

Answer: Option A

Explanation:

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15. 

The output of the 74 series of TTL gates is taken from a BST in

A. totem pole and common collector configuration
B. either totem pole or open collector configuration
C. common base configuration
D. common collector configuration

Answer: Option B

Explanation:

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