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Electronics and Communication Engineering - Digital Electronics

Exercise : Digital Electronics - Section 18
11.
In a shift register the data is loaded in one operation but shifted out one bit at a time, The shift register is
serial in-serial out
parallel in-serial out
serial in-parallel out
parallel in-parallel out
Answer: Option
Explanation:
No answer description is available. Let's discuss.
12.
In CCD
a small charge is deposited for logical 1
a small charge is deposited for both logical 1 and 0
a small charge is deposited for logical 0 and large charge for logical 1
none of the above
Answer: Option
Explanation:
No answer description is available. Let's discuss.
13.
The contents of the program counter after the call operation point to the first instruction on the
stack
subroutine
either of the above
none of the above
Answer: Option
Explanation:
No answer description is available. Let's discuss.
14.
Dual slope ADC uses an op amp comparator.
True
False
Answer: Option
Explanation:
No answer description is available. Let's discuss.
15.
The output of the 74 series of TTL gates is taken from a BST in
totem pole and common collector configuration
either totem pole or open collector configuration
common base configuration
common collector configuration
Answer: Option
Explanation:
No answer description is available. Let's discuss.
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