Electronics and Communication Engineering - Digital Electronics
Exercise :: Digital Electronics - Section 17
| 11. |
A two-input OR gate is designed for positive logic. However, it is operated with negative logic. The resulting logic operation will then be |
Answer: Option A
Explanation:
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| 12. |
A clock signal driving a 6-bit ring counter has a frequency of 1 MHz. How long is each timing bit high? |
Answer: Option A
Explanation:
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| 13. |
A twisted ring counter consisting of 4 FF will have |
| A. |
4 states | | B. |
8 states | | C. |
24 states | | D. |
None of the above |
Answer: Option B
Explanation:
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| 14. |
Assertion (A): In a serial in-serial out shift register, access is available only to the left most or right most flip flops Reason (R): If the output of a shift register is feedback to serial input it can be used as a ring counter. |
| A. |
Both A and R are correct and R is correct explanation of A | | B. |
Both A and R are correct but R is not correct explanation of A | | C. |
A is true, R is false | | D. |
A is false, R is true |
Answer: Option B
Explanation:
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| 15. |
IC counters are |
| A. |
synchronous only | | B. |
asynchronous only | | C. |
both synchronous and asynchronous | | D. |
none of the above |
Answer: Option C
Explanation:
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