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Electronics and Communication Engineering - Digital Electronics

Exercise : Digital Electronics - Section 15
16.
The fetching, decoding and executing of an instruction is broken down into several time intervals. Each of these intervals, involving one or more clock periods, is called a
instruction cycle
machine cycle
process cycle
none of the above
Answer: Option
Explanation:
No answer description is available. Let's discuss.
17.
The output of the circuit shown below will be of the frequency
125 Hz
250 Hz
500 Hz
750 Hz
Answer: Option
Explanation:
No answer description is available. Let's discuss.
18.
In the given figure Y =
A
B
A + B + C
ABC
Answer: Option
Explanation:
No answer description is available. Let's discuss.
19.

Assertion (A): An encoder converts key dips to binary code.

Reason (R): An encoder has more inputs than output.

Both A and R are correct and R is correct explanation of A
Both A and R are correct but R is not correct explanation of A
A is true, R is false
A is false, R is true
Answer: Option
Explanation:
No answer description is available. Let's discuss.
20.
If a RAM has 34 bits in its MAR and 16 bits in its MDR, then its capacity will be
32 GB
16 GB
32 MB
16 MB
Answer: Option
Explanation:
No answer description is available. Let's discuss.
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