Electronics and Communication Engineering - Digital Electronics

16. 

The fetching, decoding and executing of an instruction is broken down into several time intervals. Each of these intervals, involving one or more clock periods, is called a

A. instruction cycle
B. machine cycle
C. process cycle
D. none of the above

Answer: Option B

Explanation:

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17. 

The output of the circuit shown below will be of the frequency

A. 125 Hz
B. 250 Hz
C. 500 Hz
D. 750 Hz

Answer: Option B

Explanation:

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18. 

In the given figure Y =

A. A
B. B
C. A + B + C
D. ABC

Answer: Option B

Explanation:

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19. 

Assertion (A): An encoder converts key dips to binary code.

Reason (R): An encoder has more inputs than output.

A. Both A and R are correct and R is correct explanation of A
B. Both A and R are correct but R is not correct explanation of A
C. A is true, R is false
D. A is false, R is true

Answer: Option B

Explanation:

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20. 

If a RAM has 34 bits in its MAR and 16 bits in its MDR, then its capacity will be

A. 32 GB
B. 16 GB
C. 32 MB
D. 16 MB

Answer: Option A

Explanation:

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