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Electronics and Communication Engineering - Digital Electronics

Exercise : Digital Electronics - Section 12
26.
TTL circuit with active pull up is preferred because of its suitability for
wired AND operation
bus operated system
wired logic operation
reasonable dissipation and speed of operation
Answer: Option
Explanation:
No answer description is available. Let's discuss.
27.
A parity check usually can detect
one-bit error
double-bit error
three-bit error
any-bit error
Answer: Option
Explanation:
No answer description is available. Let's discuss.
28.
Which of the following is 'synchronous'?
Half adder
Full adder
R-S flip-flop
Clocked R-S flip-flop
Answer: Option
Explanation:
No answer description is available. Let's discuss.
29.
TRAP is __________ whereas RST 7.5, RST 6.5, RST 5.5 are __________ .
maskable, non-maskable
maskable, maskable
non-maskable, non-maskable
non-maskable, maskable
Answer: Option
Explanation:
No answer description is available. Let's discuss.
30.
For a binary half subtractor having two inputs A and B the correct sets of logical expressions for the outputs D (A - B) and X = Borrow are
D = AB + AB, X = AB
D = AB AB, X = AB
D = AB + AB, X = AB
D = AB + A B, X = AB
Answer: Option
Explanation:
No answer description is available. Let's discuss.
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