Electronics and Communication Engineering - Digital Electronics

21. 

In 2's complement addition, the carry generated in the last stage is

A. added to LSB
B. neglected
C. added to bit next to MSB
D. added to the bit next to LSB

Answer: Option B

Explanation:

No answer description available for this question. Let us discuss.

22. 

A is even or B is true. Negation of above statement is

A. A is odd or B is false
B. A is odd and B is false
C. A is even or B is false
D. A is even and B is false

Answer: Option B

Explanation:

No answer description available for this question. Let us discuss.

23. 

The abbreviation DTL stands for

A. Digital Timing Logic
B. Diode Transistor Logic
C. Dynamic Transient Logic
D. Delayed Tracking Logic

Answer: Option B

Explanation:

No answer description available for this question. Let us discuss.

24. 

Which one of the following is a D to A conversion technique?

A. Successive approximation
B. Weighted resistor
C. Dual slope
D. Single slope

Answer: Option B

Explanation:

No answer description available for this question. Let us discuss.

25. 

What is the purpose of using ALE signal high?

A. To latch low order address from bus to separate A0 - A7 lines
B. To latch data D0 - D7 from bus to separate data bus
C. To disable data bus latch
D. All of the above

Answer: Option A

Explanation:

No answer description available for this question. Let us discuss.