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Electronics and Communication Engineering - Digital Electronics

Exercise : Digital Electronics - Section 9
21.
In 2's complement addition, the carry generated in the last stage is
added to LSB
neglected
added to bit next to MSB
added to the bit next to LSB
Answer: Option
Explanation:
No answer description is available. Let's discuss.
22.
A is even or B is true. Negation of above statement is
A is odd or B is false
A is odd and B is false
A is even or B is false
A is even and B is false
Answer: Option
Explanation:
No answer description is available. Let's discuss.
23.
The abbreviation DTL stands for
Digital Timing Logic
Diode Transistor Logic
Dynamic Transient Logic
Delayed Tracking Logic
Answer: Option
Explanation:
No answer description is available. Let's discuss.
24.
Which one of the following is a D to A conversion technique?
Successive approximation
Weighted resistor
Dual slope
Single slope
Answer: Option
Explanation:
No answer description is available. Let's discuss.
25.
What is the purpose of using ALE signal high?
To latch low order address from bus to separate A0 - A7 lines
To latch data D0 - D7 from bus to separate data bus
To disable data bus latch
All of the above
Answer: Option
Explanation:
No answer description is available. Let's discuss.
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