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Electronics and Communication Engineering - Digital Electronics

Exercise : Digital Electronics - Section 7
26.
In following figure, the initial contents of the 4-bit serial in parallel out, right shift, shift register as shown in figure are 0110. After 3 clock pulses the contents of the shift register will be
0000
0101
1010
1110
Answer: Option
Explanation:

27.
For the logic circuit of the given figure, the minimized expression is
Y = A + B + C
Y = A + B
Y = ABC
Answer: Option
Explanation:

+ A + C = A + B + C + A + C = A + C + B

=

28.
Binary multiplication can be done by repeated addition.
True
False
Answer: Option
Explanation:
No answer description is available. Let's discuss.
29.

Assertion (A): In totem pole output the output impedance is low.

Reason (R): TTL gate with active pull up should not be used in wired AND connection.

Both A and R are correct and R is correct explanation of A
Both A and R are correct but R is not correct explanation of A
A is true, R is false
A is false, R is true
Answer: Option
Explanation:
No answer description is available. Let's discuss.
30.
A 4 bit synchronous counter uses flip flops with a delay time of 15 ns each. The time required for change of state is
15 ns
30 ns
45 ns
60 ns
Answer: Option
Explanation:

In a synchronous counter clock input is applied to all flip flops simultaneously. Hence total delay time is 15 ns.

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