Exercise :: Digital Electronics - Section 5
- Digital Electronics - Section 1
- Digital Electronics - Section 2
- Digital Electronics - Section 3
- Digital Electronics - Section 4
- Digital Electronics - Section 5
- Digital Electronics - Section 6
- Digital Electronics - Section 7
- Digital Electronics - Section 8
- Digital Electronics - Section 9
- Digital Electronics - Section 10
- Digital Electronics - Section 11
- Digital Electronics - Section 12
- Digital Electronics - Section 13
- Digital Electronics - Section 14
- Digital Electronics - Section 15
- Digital Electronics - Section 16
- Digital Electronics - Section 17
- Digital Electronics - Section 18
- Digital Electronics - Section 19
- Digital Electronics - Section 20
- Digital Electronics - Section 21
- Digital Electronics - Section 22
- Digital Electronics - Section 23
- Digital Electronics - Section 24
26. | In the given figure, Y = |
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Answer: Option A Explanation:
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27. | Assertion (A): The access time of memory is lowest in the case of DRAM Reason (R): DRAM uses refreshing cycle. |
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Answer: Option D Explanation: DRAM has lower speed than SRAM. |
28. | In a 3 input NOR gate, the number of states in which output is 1 equals |
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Answer: Option A Explanation: Only one input, i.e., A = 0, B = 0 and C = 0 gives 1 as output. |
29. | Assertion (A): Even if TTL gates and CMOS gates used in a realization have the same power supply of + 5 V, suitable circuit is needed to interconnect them Reason (R): VOH, VOL, VIH and VIL of a TTL gave are respectively 2.4, 0.4, 2 and 0.8 V respectively. If supply voltage is + 5 V. VIL and VIH for CMOS gate for the supply voltage of + 5 V are 1.5 V and 3.5 V respectively. |
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Answer: Option A Explanation: Interfacing is necessary and interfacing depends on gate parameters like VOH, VOL, IIH, IIL. |
30. | The series 54 H/74 H denotes |
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Answer: Option B Explanation: It denotes high speed TTL. |