Electronics and Communication Engineering - Digital Electronics

In the given figure, Y =

Assertion (A): The access time of memory is lowest in the case of DRAM

Reason (R): DRAM uses refreshing cycle.

In a 3 input NOR gate, the number of states in which output is 1 equals

Assertion (A): Even if TTL gates and CMOS gates used in a realization have the same power supply of + 5 V, suitable circuit is needed to interconnect them

Reason (R): V_OH, V_OL, V_IH and V_IL of a TTL gave are respectively 2.4, 0.4, 2 and 0.8 V respectively. If supply voltage is + 5 V. V_IL and V_IH for CMOS gate for the supply voltage of + 5 V are 1.5 V and 3.5 V respectively.

The series 54 H/74 H denotes