IndiaBIX

Digital Electronics - Flip-Flops

Exercise : Flip-Flops - General Questions
36.

The symbols on this flip-flop device indicate ________.

triggering takes place on the negative-going edge of the CLK pulse
triggering takes place on the positive-going edge of the CLK pulse
triggering can take place anytime during the HIGH level of the CLK waveform
triggering can take place anytime during the LOW level of the CLK waveform
Answer: Option
Explanation:
No answer description is available. Let's discuss.
37.
In a 555 timer, three 5 k resistors provide a trigger level of ________.
1/4 VCC and a threshold level 1/2 VCC
1/3 VCC and a threshold level 3/4 VCC
1/3 VCC and a threshold level 2/3 VCC
1/4 VCC and a threshold level 2/3 VCC
Answer: Option
Explanation:
No answer description is available. Let's discuss.
38.
Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?
active-HIGH
active-LOW
Answer: Option
Explanation:
No answer description is available. Let's discuss.
39.
The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the:
edge-detection circuit.
NOR latch.
NAND latch.
pulse-steering circuit.
Answer: Option
Explanation:
No answer description is available. Let's discuss.
40.
With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?
16
8
4
2
Answer: Option
Explanation:
No answer description is available. Let's discuss.
Quick links
Quantitative Aptitude
Verbal (English)
Reasoning
Programming
Interview
Placement Papers