Online Digital Electronics Test - Digital Electronics Test 2

Instruction:

This is a FREE online test. Beware of scammers who ask for money to attend this test.
Total number of questions: 20.
Time allotted: 30 minutes.
Each question carries 1 mark; there are no negative marks.
DO NOT refresh the page.
All the best!

How many binary bits are necessary to represent 748 different numbers?

[#]

SMT stands for small-to-medium technology.

True

False

[#]

The systems shown in the given figure transfer data ________.

serially

sequentially

in parallel

both serially and sequentially

[#]

Convert binary 11001111 to hexadecimal.

8F₁₆

CE₁₆

DF₁₆

CF₁₆

[#]

Zeros may be added to the left of the MSB to produce even groups of 4 bits when converting from binary to hexadecimal.

True

False

[#]

In binary, the decimal number 93 converts to ________ digits.

seven

eight

five

[#]

Which of the following gates has the exact inverse output of the OR gate for all possible input combinations?

NOR

NOT

NAND

AND

[#]

How many 2-input NOR gates does it take to produce a 2-input NAND gate?

[#]

A digital circuit that converts coded information into a familiar or non-coded form is known as an encoder.

True

False

[#]

10.

In VHDL, each instance of a component is given a name followed by a semicolon and the name of the library primitive.

True

False

[#]

11.

The postponed symbol (

) on the output of a flip-flop identifies it as being ________.

a D flip-flop

a J-K flip-flop

pulse triggered

trailing edge-triggered

[#]

12.

Which of the following procedures could be used to check the parallel loading feature of a counter?

Preset the LOAD inputs, set the CLR to its active level, and check to see that the Q outputs match the values preset into the LOAD inputs.

Apply LOWs to the parallel DATA inputs, pulse the CLK input, and check for LOWs on all the Q outputs.

Apply HIGHs to all the DATA inputs, pulse the CLK and CLR inputs, and check to be sure that the Q outputs are all LOW.

Apply HIGHs to all the Q terminals, pulse the CLK, and check to see if the DATA terminals now match the Q outputs.

[#]

13.

To design a divide-by-200 counter using synchronous counters, two 4-bit counters could be cascaded together to form an 8-bit counter.

True

False

[#]

14.

The refresh period for capacitors used in DRAMs is ________.

2 ms

64 ms

[#]

15.

The output of this circuit is always ________.

[#]

16.

An ALU is a multipurpose device capable of providing several different logic operations.

True

False

[#]

17.

One of the first steps in any HDL project is to define its scope by naming each input and output.

True

False

[#]

18.

In the stepper motor, the half-step sequence is used when ________.

less torque is needed

larger steps are desired

smaller steps are desirable

more torque is needed

[#]

19.

What is the difference between the 74HC00 series and the 74HCT00 series of CMOS logic?

The HCT series is faster.

The HCT series is slower.

The HCT series is input and output voltage compatible with TTL.

The HCT series is not input and output voltage compatible with TTL.

[#]

20.

Which of the following buses is primarily used to carry signals that direct other ICs to find out what type of operation is being performed?

data bus

control bus

address bus

address decoder bus

[#]

Quick links

Quantitative Aptitude

Verbal (English)

Reasoning

Programming

Interview

Placement Papers

Online Digital Electronics Test - Digital Electronics Test 2

Marks : 2/20

Test Review : View answers and explanation for this test.

Current Affairs

Interview Questions

Group Discussions