Electronics - Flip-Flops and Timers - Discussion
Discussion Forum : Flip-Flops and Timers - General Questions (Q.No. 2)
2.
When both inputs of a J-K flip-flop cycle, the output will:
Discussion:
13 comments Page 2 of 2.
Vihari said:
1 decade ago
Toggle condition when the J-K flip flop receives the both the inputs as high and clock is also in rise edge the output of the flip flop will be changes to 0 and 1.
It will not be constant constant output for every clock cycle it will race in between 1/0/1/0.
It will not be constant constant output for every clock cycle it will race in between 1/0/1/0.
Prashanth said:
5 years ago
When it cycles like j=1and k=0 then how it becomes no change, It becomes set condition right?
AL from M.U. said:
4 years ago
Cycle = 2 x toggle.
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