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Electronics - Flip-Flops and Timers

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Exercise : Flip-Flops and Timers - General Questions
1.
Which of the following is correct for a gated D-type flip-flop?
The Q output is either SET or RESET as soon as the D input goes HIGH or LOW.
The output complement follows the input when enabled.
Only one of the inputs can be HIGH at a time.
The output toggles if one of the inputs is held HIGH.
Answer: Option
Explanation:
No answer description is available. Let's discuss.
2.
When both inputs of a J-K flip-flop cycle, the output will:
be invalid
not change
change
toggle
Answer: Option
Explanation:
No answer description is available. Let's discuss.
3.
Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
asynchronous operation
low input voltages
gate impedance
cross coupling
Answer: Option
Explanation:
No answer description is available. Let's discuss.
4.
The 555 timer can be used in which of the following configurations?
astable, monostable
monostable, bistable
astable, toggled
bistable, tristable
Answer: Option
Explanation:
No answer description is available. Let's discuss.
5.
A basic S-R flip-flop can be constructed by cross-coupling which basic logic gates?
AND or OR gates
XOR or XNOR gates
NOR or NAND gates
AND or NOR gates
Answer: Option
Explanation:
No answer description is available. Let's discuss.
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