Electronics - Flip-Flops and Timers - Discussion

1. 

Which of the following is correct for a gated D-type flip-flop?

[A]. The Q output is either SET or RESET as soon as the D input goes HIGH or LOW.
[B]. The output complement follows the input when enabled.
[C]. Only one of the inputs can be HIGH at a time.
[D]. The output toggles if one of the inputs is held HIGH.

Answer: Option A

Explanation:

No answer description available for this question.

Vimal said: (Oct 15, 2010)  
Clock should be active.

Karuppasamy Kpk said: (Jul 5, 2011)  
Option 'A' is correct,

In D flip flop, when the clock is high then the out depends on the input otherwise reminds previous output.

In a state of clock high, when D is high the output Q also high, if D is '0' then output also zero.

Option B is the state of T flip flop.
Option C is wrong becoz D flip flop have a single input.
Option D also wrong bcoz D filp flop hav a single i/p

Kalyan said: (Sep 22, 2011)  
Output of the D flip flop changes only at the falling edge of the clock.

What is said by karuppasamy is wrong.

D is high or low the output is only responded at falling edge of clock.

You can also refer animation in play-hookey website. The explanation was nice.

Priyanka said: (Sep 30, 2014)  
In D flip-flop output changes as per input set or reset and it is independent of clock.

Vihari said: (Dec 5, 2014)  
In the above question they have not mention of active low or active high flip flop. So we generally considered as the active high clock means the circuit operate on rise edge of the clock.

Vineet Pandya said: (Oct 5, 2015)  
Why on the earth is everybody thinking about clock? Of course the clock must be high that the D-f/f is working.

Now, D-f/f is also called TRANSPARENT FLIP FLOP. Since it gives the same value in the output as in the input.

[input=D, output=Q].

D=0, Q=0.

D=1, Q=1.

This is the condition of option(A).

Now read (A) option carefully:

"The Q output is either SET(1) or RESET(0) as soon as the D input goes HIGH(1) or LOW(0)".

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