Electronics - Flip-Flops and Timers - Discussion

Discussion Forum : Flip-Flops and Timers - General Questions (Q.No. 2)
2.
When both inputs of a J-K flip-flop cycle, the output will:
be invalid
not change
change
toggle
Answer: Option
Explanation:
No answer description is available. Let's discuss.
Discussion:
13 comments Page 1 of 2.

Guru said:   1 decade ago
@Sundar clue is correct but small changes.

After one cycle the value of each input comes to the same value
ex: Assume J=0 and K=1.

After 1 cycle, it becomes as J=0->1->0(1 cycle complete) and K=1->0->1(1 cycle complete).

So answer is B. not change o/p.

Vihari said:   1 decade ago
Toggle condition when the J-K flip flop receives the both the inputs as high and clock is also in rise edge the output of the flip flop will be changes to 0 and 1.

It will not be constant constant output for every clock cycle it will race in between 1/0/1/0.

Ravi sinha said:   1 decade ago
Q(next state)=JQ^+K^Q.
so the truth table of J K flip flop will be :-
J K Q(next state)
0 0 no change(Q)
0 1 reset(0)
1 0 set(1)
1 1 toggle(Q^)

Adil said:   1 decade ago
@Ravi sinha tabe is right. When they form in cycle they form in 1 & 0 so output become no change.

Prashanth said:   5 years ago
When it cycles like j=1and k=0 then how it becomes no change, It becomes set condition right?

Govind singh said:   1 decade ago
I think correct answer is toggle because at 11 position jk toggle
(1)

Sundar said:   1 decade ago
Assume J=0 and K=1

When cycle it, it becomes as J=1 and K=0.

Asheer said:   1 decade ago
What is the meaning of inputs of j k flipflop cycle?

Anaya said:   1 decade ago
Then there will be change how answer is no change.
(2)

Ravikanth said:   1 decade ago
@Bhuji.

Toggle means complement.
(1)


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