Electronics - Field Effect Transistors (FET) - Discussion

*N-type JFET is operated with VGS<=0; (i.e., reverse gate to source).
* VGS controls ID.

When VGS=0, IDSS=maximum current.
Assuming, initially, VGS=0;

Option A:

Now if we decrease VGS (more negative), then ID decreases; (Option A is correct only if we are given assumption " Assuming, initially, VGS=0;". Note, A and B are giving same meaning if this assumption is not considered.)

Option B:

Increasing VGS(greater than 0), will not increase current as N-channel JFET requires negative VGS for its operation (and thus for to be in constant current region for any VGS.)
Option C and D cannot be correct as VGS controls ID. In constant-current region, current is constant wrt VDS and not VGS.

The pinch-off voltage for an N-channel JFET is 4V. When VGS=1V, lVDS(min)l at which pinch-off occurs is equal to

Option D is correct.

In according to the JFET graph,

1.Linear region
2.Pinch off region
3.Cutt off region

1.Linear region - Gate source voltage increases the drain current also increases.
2.Pinch off region - In which gate-source voltage, the drain current become zero the voltage is known as pinch off.
3.Cutt off region - After the pinch-off region the gate is not dependent the gate-source voltage.

Answer is correct because characteristic plot between Id and Vds so that according to this if Vds increases then id remains constant.

But here if we want to decrease the current Id then Vgs will be decreased.

In n channel vgs is negative if vgs increase in more -ve I'd decrease. But vgs decrease I'd automatically increase.

Answer is 1.

As channel depends on Vgs and Ids depends on channel. So we can say Ids is proportional to Vgs.

Both A and D are correct as for me. Because in constant region Ids remains constant till breakdown region occurs.

As the drain to source voltage is increased this depletion region also widens narrowing down the channel at point both the regions touch pinching off the channel, the drain current increases linearly at first but after pinch off voltage it becomes constant.

As Vgs (reverse bias voltage gate to source) increases Id decreases because increase in Vgs causes to increase the depletion region and reduce the effective width of the channel so Id will decreases. And if we made Vgs positive Id will remain constant for n channel JFET.

When Vgs increases like 0v, 1v, 2v... Id also increases. According to the graph that we plot Id vs Vds as a function of Vgs.