Discussion :: Field Effect Transistors (FET) - General Questions (Q.No.7)
|Viswajith said: (Sep 5, 2011)|
|Yes as VGS decreases ID decreases but also when VGS increases ID remains constant so I think option D is also correct.|
|Abdul said: (Feb 13, 2012)|
|The correct option is D. Because constant current region means saturation region, so as Vgs increases Id remains constant.|
|Ar Abhinav said: (Apr 27, 2012)|
|This is simple explanation that depends on the depletion region, as Vgs increases, it tend to increase the depletion region. As the depletion region decreases it tends to allow less electrons flow through the channel, as the number of electrons flowing through the channel decreases then current also decreases.|
|Raviteja S said: (Oct 9, 2012)|
|When Vgs increases like 0v, 1v, 2v... Id also increases. According to the graph that we plot Id vs Vds as a function of Vgs.|
|Sainath said: (Dec 7, 2013)|
|As Vgs (reverse bias voltage gate to source) increases Id decreases because increase in Vgs causes to increase the depletion region and reduce the effective width of the channel so Id will decreases. And if we made Vgs positive Id will remain constant for n channel JFET.|
|Ramesh Ren said: (Jul 25, 2014)|
|As the drain to source voltage is increased this depletion region also widens narrowing down the channel at point both the regions touch pinching off the channel, the drain current increases linearly at first but after pinch off voltage it becomes constant.|
|Aarth said: (Nov 22, 2014)|
|Both A and D are correct as for me. Because in constant region Ids remains constant till breakdown region occurs.|
|Abu Sayeed said: (Nov 24, 2014)|
|Answer is 1.
As channel depends on Vgs and Ids depends on channel. So we can say Ids is proportional to Vgs.
|Vardaman said: (Sep 25, 2016)|
|In n channel vgs is negative if vgs increase in more -ve I'd decrease. But vgs decrease I'd automatically increase.|
|Pankky said: (Apr 28, 2017)|
|Answer is correct because characteristic plot between Id and Vds so that according to this if Vds increases then id remains constant.
But here if we want to decrease the current Id then Vgs will be decreased.
|Mohan said: (May 21, 2017)|
|Option D is correct.
In according to the JFET graph,
2.Pinch off region
3.Cutt off region
1.Linear region - Gate source voltage increases the drain current also increases.
2.Pinch off region - In which gate-source voltage, the drain current become zero the voltage is known as pinch off.
3.Cutt off region - After the pinch-off region the gate is not dependent the gate-source voltage.
|Sri said: (Oct 11, 2019)|
|The pinch-off voltage for an N-channel JFET is 4V. When VGS=1V, lVDS(min)l at which pinch-off occurs is equal to|
|Smurtza said: (Nov 28, 2019)|
|*N-type JFET is operated with VGS<=0; (i.e., reverse gate to source).
* VGS controls ID.
When VGS=0, IDSS=maximum current.
Assuming, initially, VGS=0;
Now if we decrease VGS (more negative), then ID decreases; (Option A is correct only if we are given assumption " Assuming, initially, VGS=0;". Note, A and B are giving same meaning if this assumption is not considered.)
Increasing VGS(greater than 0), will not increase current as N-channel JFET requires negative VGS for its operation (and thus for to be in constant current region for any VGS.)
Option C and D cannot be correct as VGS controls ID. In constant-current region, current is constant wrt VDS and not VGS.
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