Electronics and Communication Engineering - Exam Questions Papers

46. 

Refer to the NAND and NOR latches shown in the figure. The inputs (P1, P2) for both the latches are first made (0, 1) and then, after a few seconds, made (1, 1). The corresponding stable outputs (Q1, Q2) are

A. NAND: first (0, 1) then (0, 1) NOR: first (1, 0) then (0, 0)
B. NAND: first (1, 0) then (1, 0) NOR: first (1, 0) then (1, 0)
C. NAND: first (1, 0) then (1, 0) NOR: first (1, 0) then (0, 0)
D. NAND: first (1, 0) then (1, 1) NOR: first (0, 1) then (0, 1)

Answer: Option C

Explanation:

No answer description available for this question. Let us discuss.

47. 

Consider the following two statements about the internal conditions in an n-channel MOSFET operating in the active region
S1: The inversion charge decreases from source to drain
S2: The channel potential increases from source to drain
Which of the following is correct?

A. Only S2 is true
B. Both S1 and S2 are false
C. Both S1 and S2 are true, but S2 is not a reason for S1
D. Both S1 and S2 are true, and S2 is a reason for S1

Answer: Option D

Explanation:

No answer description available for this question. Let us discuss.

48. 

The wavelength of a wave with propagation constant (0.1p + j0.4p)m-1 is

A. 5 m
B. 5p m
C.
D. 10 m

Answer: Option A

Explanation:

γ = a + jβ

β = 0.4p


49. 

For what positive value of K does the polynomial s4 + 8s3 + 24s2 + 32s + K have roots with zero real parts?

A. 10
B. 20
C. 40
D. 80

Answer: Option D

Explanation:

No answer description available for this question. Let us discuss.

50. 

Which of the following capabilities are available in a Universal Shift Register?

  1. Shift left
  2. Shift right
  3. Parallel load
  4. Serial add
Select the correct answer from the codes given below:

A. 2 and 4 only
B. 1, 2 and 3
C. 1, 2 and 4
D. 1, 3 and 4

Answer: Option B

Explanation:

No answer description available for this question. Let us discuss.

« Prev   1 2 3 4 5 6 7 8 9 10