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Electronic Devices - DC Biasing-FETs

Exercise : DC Biasing-FETs - Filling the Blanks
11.
In a feedback-bias configuration, the slope of the dc load line is controlled by ________.
RG
RD
VDG
None of the above
Answer: Option
Explanation:
No answer description is available. Let's discuss.
12.
For R2 smaller than ________ k the voltage VD is equal to VDD = 16 V.

3.75
5
12.0
24
Answer: Option
Explanation:
No answer description is available. Let's discuss.
13.
In a depletion-type MOSFET, the transfer characteristic rises ________ as VGS becomes more positive.
less rapidly
more rapidly
the same
None of the above
Answer: Option
Explanation:
No answer description is available. Let's discuss.
14.
The dc load line is drawn using the equation obtained by applying Kirchhoff's voltage law (KVL) at ________ side loop(s) of the circuit.
the output
the input
both the input and output
None of the above
Answer: Option
Explanation:
No answer description is available. Let's discuss.
15.
In a universal JFET bias curve, the vertical scale labeled m is used to find the solution to the ________ configuration.
fixed-bias
self-bias
voltage-divider
None of the above
Answer: Option
Explanation:
No answer description is available. Let's discuss.
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