Digital Electronics - Logic Gates - Discussion

In this situation consider 3 inputs NAND gate.
for instance,

Where X column is the result and A B C are inputs,

A B C X
0 0 0 1
0 0 1 1
1 0 0 1
0 1 0 1
1 1 0 1
0 1 1 1
1 1 1 0

For every low input, there will be a high output.
Therefore it satisfies the given condition.

It cannot be nor, as it both the input need to low or high as the same time, not nor will not be an option, only left with Nand as one input should be low at the time which is mentioned in the here.

Why can't it be ex-or?

@Ethan.

Check the answer using two inputs it also gives the same answer that I explain using three inputs.

Considering the truth table of NAND gate.
A B OUTPUT
0 0 1
0 1 1
1 0 1
1 1 0 = here we get the output HIGH when the two inputs are LOW.

Considering the truth table for OR gate.
A B OUTPUT
0 0 0
0 1 1
1 0 1
1 1 1 = here the output is HIGH when the two inputs are HIGH.

BUT question said first input must be LOW when the output is HIGH. So we can't get OR gate as the answer.

According to me, Both Nand and OR gates are correct.

Drawing table:

A - B AND NAND OR NOR
0 - 0 --->0 1 0 1
0 - 1 --->0 1 1 0
1 - 0 --->0 1 1 0
1 - 1 --->1 0 1 0

Now let us take attention here in this table which will clear all the confusion.

Expression:- y = A. B.

0 0 = 1 (high).
0 1 = 1 (high).
1 0 = 1 (high).
1 1 = 0 (low).

It combination of "AND" gate followed by "NOT" gate it is reverse operation of "AND" gate.

If both inputs are high output is low, if any one input is low output is high.

Expression:- y=A. B.

0 0=1 (high).

0 1=1 (high).

1 0=1 (high).

1 1=0 (low).

The simple answer would be to combat the confusion between NAND and OR that whenever there is an i/p signal at 0 the o/p must be 1, whatever be the 2nd i/p.

Simply inhibited low signal as a input means one input is fixed that is 0 what ever may be the 2nd input out is constant for that combination i.e. NAND gate check it by drawing NAND gate diagram then it is more clear.