Digital Electronics - Logic Gates - Discussion


If a signal passing through a gate is inhibited by sending a LOW into one of the inputs, and the output is HIGH, the gate is a(n):

[A]. AND
[C]. NOR
[D]. OR

Answer: Option B


No answer description available for this question.

P.Narendra Kumar said: (Dec 27, 2010)  
In question he is not discussed about second input .we can take second input as a dont care if we apply the 0&dont care combination NAND gate will give the high output

Mayphics said: (Jun 29, 2011)  
Ok, then can anyone explain how its not NOR.

Madhu Badavath said: (Jul 19, 2011)  

Consider one situation that if you apply 2 inputs to NOR gate in that one of the input is LOW(i,e 0)..

Then the OUTPUT is entirely depends on the second input which will you provide.......

means ,,,,,,,2 Conditions here

1.IF second input is LOW(0) Then OUTPUT of the NOR gate is HIGH(1)

2.IF second input is HIGH(1), then OUTPUT of NOR gate Iis LOW(0)

But in this question we req. OUTPUT SHOULD be HIGH means OUTPUT independent of INPUT.......

So ANSWER is NAND GATE........

R S Dayal said: (Sep 4, 2011)  
Here second input is not given, then we can take any i/p. 0 or 1.

Prasant said: (Feb 3, 2012)  
In nor gate if one input is 0, and other is 1, then the output will be 0. If both input are low then the o/p is 1, so we conform that nor gate is not the answer but in nand gate if one input is 0 and other is either 0 or 1, the output is high. So the answer is nanad gate.

Krishna said: (Mar 1, 2012)  
Can any one say why it is not OR?

Vinashi Jindal said: (Mar 7, 2012)  
Why it is NAND gate not NOR gate?

Mehak said: (Mar 31, 2012)  
Hey when we give 1 low input and get high output the OR gate also gives the same result. So why it is only NAND gate not OR gate?

Jai said: (Jun 1, 2012)  
In OR gate, if one input is zero and the other is 1, then O/P is 1. If both I/P's are 0, then O/P is 0. So the answer is NAND gate because in NAND gate if one I/P is 0 and the other is either 0 or 1, then O/P will be 1.

Madhu Badavath said: (Jul 27, 2012)  

NOR GATE means if any of the INPUT is HIGH OUTPUT is LOW.
But here condition is ONE of the INPUT is low and OUTPUT should be HIGH.
Its not valid in NOR GATE.
SO NAND-GATE will satisfy above condtion in all cases.
0 0 0 1 0 1
0 1 0 1 1 0

From above table we can say answer is NAND-GATE(By-Default A=0, and B=0 or 1, o/p of NAND-GATE is HIGH only).

Madhu Badavath said: (Jul 27, 2012)  


1.If second gate I/P is low, then OR-GATE O/P is LOW.

2.If Second gate I/P is HIGH, then OR-GATE O/P is HIGH.

Then our condition won't satisfy.

Kalai said: (Sep 26, 2012)  
0 0 1
0 1 1
1 0 1
1 1 0

Shobi said: (Feb 22, 2013)  
First fix the any one i/p = 0.

Then whatever i/p given to the second pin always lead to high , so

pin1 pin2 o/p(nand)
0 0 1
0 1 1

So even 1 i/p is low o/p will be high in NAND.

Sarvesh said: (Nov 14, 2013)  
If a signal passing through a gate is inhibited by sending a LOW into one of the inputs, and the output is HIGH, the gate is a(n):

Here already signal is passing through the gate, it is inhibited by applying a low into one of its inputs, that means now the two inputs are low, and the output is high so it may be either NAND or NOR.

Rajashekar said: (Nov 23, 2013)  
If signal passing through a gate is inhibited by sending a LOW into one of the those inputs then output is HIGH.

Because of at least one of the input is low then output is high of the nand gate.

Ankit said: (Jul 31, 2014)  
NAND - if any one of input is low than output is high.
In OR if both input is low than output is low.

So here only one input is specified which is low, and output is high so NAND gate.

Bayaw said: (Oct 27, 2014)  
Take this for instance. (i.e. Input A-1 Input B-0)

OR 1 + 0 = 1 (NOT) = 0 (logic low) ----> NOR.
AND 1 x 0 = 0 (NOT) = 1 (logic high)----> NAND.

Kuldeep Nagar said: (Feb 21, 2015)  
But in OR gate if we use 0 and 1 as input then output is also high. Why B is correct answer? D can be answer.

Arun said: (Apr 11, 2015)  

Here one input is low and another would be high or low. In both cases i.e.either in (0, 1) or in (0, 0) the output should be high. And this condition satisfy by NAND gate.

Krishna said: (Jun 9, 2015)  
Simply inhibited low signal as a input means one input is fixed that is 0 what ever may be the 2nd input out is constant for that combination i.e. NAND gate check it by drawing NAND gate diagram then it is more clear.

Suhani Thakur said: (Dec 30, 2015)  
The simple answer would be to combat the confusion between NAND and OR that whenever there is an i/p signal at 0 the o/p must be 1, whatever be the 2nd i/p.

Simran said: (Aug 2, 2016)  
It combination of "AND" gate followed by "NOT" gate it is reverse operation of "AND" gate.

If both inputs are high output is low, if any one input is low output is high.

Expression:- y=A. B.

0 0=1 (high).

0 1=1 (high).

1 0=1 (high).

1 1=0 (low).

Binodini Das said: (Aug 27, 2016)  
Expression:- y = A. B.

0 0 = 1 (high).
0 1 = 1 (high).
1 0 = 1 (high).
1 1 = 0 (low).

Shekhar Chaudhary said: (Sep 2, 2016)  
Drawing table:

0 - 0 --->0 1 0 1
0 - 1 --->0 1 1 0
1 - 0 --->0 1 1 0
1 - 1 --->1 0 1 0

Now let us take attention here in this table which will clear all the confusion.

Ethan said: (Jan 23, 2017)  
According to me, Both Nand and OR gates are correct.

Nimasha said: (Mar 30, 2017)  

Check the answer using two inputs it also gives the same answer that I explain using three inputs.

Considering the truth table of NAND gate.
0 0 1
0 1 1
1 0 1
1 1 0 = here we get the output HIGH when the two inputs are LOW.

Considering the truth table for OR gate.
0 0 0
0 1 1
1 0 1
1 1 1 = here the output is HIGH when the two inputs are HIGH.

BUT question said first input must be LOW when the output is HIGH. So we can't get OR gate as the answer.

Abhijeet Neog said: (Jun 25, 2017)  
Why can't it be ex-or?

Atul said: (Jun 28, 2018)  
It cannot be nor, as it both the input need to low or high as the same time, not nor will not be an option, only left with Nand as one input should be low at the time which is mentioned in the here.

Anon said: (Jan 1, 2020)  
In this situation consider 3 inputs NAND gate.
for instance,

Where X column is the result and A B C are inputs,

0 0 0 1
0 0 1 1
1 0 0 1
0 1 0 1
1 1 0 1
0 1 1 1
1 1 1 0

For every low input, there will be a high output.
Therefore it satisfies the given condition.

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