Digital Electronics - Logic Gates - Discussion
Discussion Forum : Logic Gates - General Questions (Q.No. 3)
3.
If a signal passing through a gate is inhibited by sending a LOW into one of the inputs, and the output is HIGH, the gate is a(n):
Discussion:
29 comments Page 2 of 3.
Arun said:
1 decade ago
TAKE THIS IS IN CONSIDERATION.
Here one input is low and another would be high or low. In both cases i.e.either in (0, 1) or in (0, 0) the output should be high. And this condition satisfy by NAND gate.
Here one input is low and another would be high or low. In both cases i.e.either in (0, 1) or in (0, 0) the output should be high. And this condition satisfy by NAND gate.
Kuldeep nagar said:
1 decade ago
But in OR gate if we use 0 and 1 as input then output is also high. Why B is correct answer? D can be answer.
Bayaw said:
1 decade ago
Take this for instance. (i.e. Input A-1 Input B-0)
OR 1 + 0 = 1 (NOT) = 0 (logic low) ----> NOR.
AND 1 x 0 = 0 (NOT) = 1 (logic high)----> NAND.
OR 1 + 0 = 1 (NOT) = 0 (logic low) ----> NOR.
AND 1 x 0 = 0 (NOT) = 1 (logic high)----> NAND.
(1)
Ankit said:
1 decade ago
NAND - if any one of input is low than output is high.
But.
In OR if both input is low than output is low.
So here only one input is specified which is low, and output is high so NAND gate.
But.
In OR if both input is low than output is low.
So here only one input is specified which is low, and output is high so NAND gate.
Rajashekar said:
1 decade ago
If signal passing through a gate is inhibited by sending a LOW into one of the those inputs then output is HIGH.
Because of at least one of the input is low then output is high of the nand gate.
Because of at least one of the input is low then output is high of the nand gate.
Sarvesh said:
1 decade ago
If a signal passing through a gate is inhibited by sending a LOW into one of the inputs, and the output is HIGH, the gate is a(n):
Here already signal is passing through the gate, it is inhibited by applying a low into one of its inputs, that means now the two inputs are low, and the output is high so it may be either NAND or NOR.
Here already signal is passing through the gate, it is inhibited by applying a low into one of its inputs, that means now the two inputs are low, and the output is high so it may be either NAND or NOR.
Shobi said:
1 decade ago
First fix the any one i/p = 0.
Then whatever i/p given to the second pin always lead to high , so
pin1 pin2 o/p(nand)
0 0 1
0 1 1
So even 1 i/p is low o/p will be high in NAND.
Then whatever i/p given to the second pin always lead to high , so
pin1 pin2 o/p(nand)
0 0 1
0 1 1
So even 1 i/p is low o/p will be high in NAND.
Kalai said:
1 decade ago
A B O/P
0 0 1
0 1 1
1 0 1
1 1 0
0 0 1
0 1 1
1 0 1
1 1 0
Madhu Badavath said:
1 decade ago
@Mehak.
IF one the I/P is low,then OR-GATE OUT COMPLETELY DEPENDS ON SECOND I/P only.
1.If second gate I/P is low, then OR-GATE O/P is LOW.
2.If Second gate I/P is HIGH, then OR-GATE O/P is HIGH.
Then our condition won't satisfy.
IF one the I/P is low,then OR-GATE OUT COMPLETELY DEPENDS ON SECOND I/P only.
1.If second gate I/P is low, then OR-GATE O/P is LOW.
2.If Second gate I/P is HIGH, then OR-GATE O/P is HIGH.
Then our condition won't satisfy.
Madhu Badavath said:
1 decade ago
@Krishna.
NOR GATE means if any of the INPUT is HIGH OUTPUT is LOW.
But here condition is ONE of the INPUT is low and OUTPUT should be HIGH.
Its not valid in NOR GATE.
SO NAND-GATE will satisfy above condtion in all cases.
A B AND NAND OR NOR
0 0 0 1 0 1
0 1 0 1 1 0
From above table we can say answer is NAND-GATE(By-Default A=0, and B=0 or 1, o/p of NAND-GATE is HIGH only).
NOR GATE means if any of the INPUT is HIGH OUTPUT is LOW.
But here condition is ONE of the INPUT is low and OUTPUT should be HIGH.
Its not valid in NOR GATE.
SO NAND-GATE will satisfy above condtion in all cases.
A B AND NAND OR NOR
0 0 0 1 0 1
0 1 0 1 1 0
From above table we can say answer is NAND-GATE(By-Default A=0, and B=0 or 1, o/p of NAND-GATE is HIGH only).
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