Digital Electronics - Flip-Flops - Discussion
Discussion Forum : Flip-Flops - General Questions (Q.No. 33)
33.
In VHDL, how many inputs will a primitive JK flip-flop have?
Discussion:
13 comments Page 1 of 2.
Jay said:
1 decade ago
How 5? Ans should be 3. J, k and clk.
Pooja said:
1 decade ago
Answer is rite. One input is j, then k, other from output of Q to j then from Q', last one is clk.
Avinash said:
1 decade ago
But they ask question for input not output then how the answer is 5?
Shiva said:
1 decade ago
@pooja:well said
Deepak said:
1 decade ago
J K flip flop takes past output as input. So Q and Q' is also a input counting to total 5.
Sony said:
1 decade ago
In VHDL program we draw j, not (j) , k, not (k) and clk signal totallly 5 input signals.
Shijubaby said:
1 decade ago
VHDL program
Entity jk is
port(j:in std_logic;
k:in std_logic;
Q:out std_logic;
Qbar:out std_logic;
clk:in std_logic);
Don't specify feedback Q and Qbar as input in Architecture behavioral SO Answer is 3
Entity jk is
port(j:in std_logic;
k:in std_logic;
Q:out std_logic;
Qbar:out std_logic;
clk:in std_logic);
Don't specify feedback Q and Qbar as input in Architecture behavioral SO Answer is 3
Balakrishna said:
1 decade ago
Based on IC design inputs : j, k, clock, clear, preset) (i.e 5 inputs).
Generally we will consider 3 input (j, k, clock) or 4 inputs (j, k, clock, clear).
Generally we will consider 3 input (j, k, clock) or 4 inputs (j, k, clock, clear).
Khitab said:
1 decade ago
I think it is because they will consider two inputs of Asynchronous JK FF as well.
Damu said:
1 decade ago
What is meant by VHDL?
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