Digital Electronics - Flip-Flops - Discussion

Discussion Forum : Flip-Flops - General Questions (Q.No. 33)
33.
In VHDL, how many inputs will a primitive JK flip-flop have?
2
3
4
5
Answer: Option
Explanation:
No answer description is available. Let's discuss.
Discussion:
13 comments Page 1 of 2.

Sumathi said:   7 years ago
It is 3 inputs.

1.j.
2.k.
3.clk.

Raj said:   9 years ago
I think that five inputs are j, k, clk, preset, clear in VHDL.

VHDL -- VHIC Hardware Description Language.
VHSIC-- Very High-Speed Integrated Circuits.

Pandey said:   9 years ago
@Damu.

VHDL is the hardware description language used in electronic design automation to describe digital and mixed-signal systems.

Damu said:   1 decade ago
What is meant by VHDL?

Khitab said:   1 decade ago
I think it is because they will consider two inputs of Asynchronous JK FF as well.

Balakrishna said:   1 decade ago
Based on IC design inputs : j, k, clock, clear, preset) (i.e 5 inputs).

Generally we will consider 3 input (j, k, clock) or 4 inputs (j, k, clock, clear).

Shijubaby said:   1 decade ago
VHDL program

Entity jk is
port(j:in std_logic;
k:in std_logic;
Q:out std_logic;
Qbar:out std_logic;
clk:in std_logic);

Don't specify feedback Q and Qbar as input in Architecture behavioral SO Answer is 3

Sony said:   1 decade ago
In VHDL program we draw j, not (j) , k, not (k) and clk signal totallly 5 input signals.

Deepak said:   1 decade ago
J K flip flop takes past output as input. So Q and Q' is also a input counting to total 5.

Shiva said:   1 decade ago
@pooja:well said


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