Digital Electronics - Flip-Flops - Discussion
Discussion Forum : Flip-Flops - General Questions (Q.No. 27)
27.
A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.
Discussion:
25 comments Page 3 of 3.
Rajesh Koothrappali said:
7 years ago
Very useful, Thanks for it @Jay.
M.DHANA said:
6 years ago
Why we are getting toggle state in J-K flip flop? Why it is coming in that state?
Please tell me.
Please tell me.
Rohu said:
6 years ago
Thaks @Jay.
Farhan said:
5 years ago
The flip flop is sensitive only to the positive or negative edge of the clock pulse. So, the flip-flop toggles whenever the clock is falling/rising at edge. This triggering of flip-flop during the transition state, is known as Edge-triggered flip-flop. Thus, the output curve has a time period twice that of the clock. Frequency is inversely related to time period and hence frequency gets halved.
Dharani said:
3 years ago
Well explanation, Thankyou so much @Jay.
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