Digital Electronics - Flip-Flops - Discussion

When j=k=1 the output toggles more than once for a single clock pulse. This phenomena is called racing in a jk flip flop. In question j=k=1 and output must toggle for more than once. So any frequency less than 20khz is correct 20khz is principle value.

As ff has 2 states I think 20/2=10khz is correct and toggling continuously from 0 to 1 makes a square wave and so it will be a square wave of <20khz. To eliminate this racing the pulse width of flip flop must be greater than propagation delay.

Well explanation, Thankyou so much @Jay.

The flip flop is sensitive only to the positive or negative edge of the clock pulse. So, the flip-flop toggles whenever the clock is falling/rising at edge. This triggering of flip-flop during the transition state, is known as Edge-triggered flip-flop. Thus, the output curve has a time period twice that of the clock. Frequency is inversely related to time period and hence frequency gets halved.

Thaks @Jay.

Why we are getting toggle state in J-K flip flop? Why it is coming in that state?

Please tell me.

Very useful, Thanks for it @Jay.

Thankyou @Jay.

@Jay.

I understand very well, Thank you.

@Satyapriya.

You may be wrong because your answer is not defined, what are you input applied?

When J = 1 and K = 1 outputs of JK flip flop are:

A) Qn+1=0
B) Qn+1=1
C) Qn+1=Q
D) Qn+1=Q\'

Give me the answer of this question.