Digital Electronics - Flip-Flops - Discussion

j=0 , k=0------------> No change state.
j=1 , k=0------------> Set condition means output = 1.
j=0 , k=1------------> Reset condition means output = 0.
j=1 , k=1 -----------> Toggle.

What will happen to the output frequency if j=0 and k=0?

When j=k=1 the output toggles more than once for a single clock pulse. This phenomena is called racing in a jk flip flop. In question j=k=1 and output must toggle for more than once. So any frequency less than 20khz is correct 20khz is principle value.

As ff has 2 states I think 20/2=10khz is correct and toggling continuously from 0 to 1 makes a square wave and so it will be a square wave of <20khz. To eliminate this racing the pulse width of flip flop must be greater than propagation delay.

O/p frequency = i/p freq / 2^n ; where n is the number of F/Fs used.

Jk flip-flop has 2 flipflop s master and slave so according to that,

Op freq = 20 / 2^1 ; 2^ (n-1) < n > 2^n.

= 10 Hz.

Here, there is no mention of master-slave jk flip-flop (has 2 flip-flops ), its just jk flip-flop(just 1 flip-flop) so therefore, there is only one flip-flop.

O/p freq = i/p freq /2^n ; n=1.
= 20 / 2 = 10 Hz.

Excellent @Shreyas.

When J = 1 and K = 1 outputs of JK flip flop are:

A) Qn+1=0
B) Qn+1=1
C) Qn+1=Q
D) Qn+1=Q\'

Give me the answer of this question.

@Satyapriya.

You may be wrong because your answer is not defined, what are you input applied?

@Jay.

I understand very well, Thank you.

Thankyou @Jay.