Digital Electronics - Flip-Flops
Exercise : Flip-Flops - True or False
- Flip-Flops - General Questions
- Flip-Flops - True or False
- Flip-Flops - Filling the Blanks
26.
Generally, a flip-flop's hold time is short enough so that its output will go to a state determined by the logic levels present at its synchronous control inputs just prior to the active clock transition.
27.
The J-K flip-flop eliminates the invalid state by toggling when both inputs are high and the clock transitions.
28.
A D-type latch is able to change states and "follow" the D input regardless of the level of the ENABLE input.
29.
A positive edge-triggered flip-flop changes states with a HIGH-to-LOW transition on the clock input.
30.
When using edge-triggered flip-flops, the data is entered into the flip-flop on the leading edge of the clock, but the output does not change until the trailing edge of the clock.
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