Electronics - Logic Gates - Discussion
Discussion Forum : Logic Gates - General Questions (Q.No. 2)
2.
If a signal passing through a gate is inhibited by sending a low into one of the inputs, and the output is HIGH, the gate is a(n):
Discussion:
18 comments Page 1 of 2.
Rita said:
10 years ago
Its is NAND gate but nt OR gate because:
NAND gate.
--------------
a b y
0 0 1 <---
0 1 1.
1 0 1.
1 1 o.
OR gate.
-----------
a b y.
0 0 0 <---
0 1 1.
1 0 1.
1 1 1.
If you observe both truth table you will get to know.
We are sending a low into one of the input and other may be one or zero but the output must be HIGH.
It's only in NANA GATE 111.
NAND gate.
--------------
a b y
0 0 1 <---
0 1 1.
1 0 1.
1 1 o.
OR gate.
-----------
a b y.
0 0 0 <---
0 1 1.
1 0 1.
1 1 1.
If you observe both truth table you will get to know.
We are sending a low into one of the input and other may be one or zero but the output must be HIGH.
It's only in NANA GATE 111.
(2)
Fembright said:
9 years ago
NOT gate inhibit the action of AND gate, and OR gate is not inhibit by any other gate so B is the answer.
(1)
Getaneh alehegn said:
1 decade ago
Of course, NAND gate also the answer but OR gate also satisfy the conditions. Because OR gate has low output if all inputs are low!
x y x+y
0 0 0
0 1 1
1 0 1
1 1 1
x y x+y
0 0 0
0 1 1
1 0 1
1 1 1
(1)
Sanjida said:
1 decade ago
i/p1 i/p2 AND NAND
----------------------------
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
NAND is NOT of AND gate.
----------------------------
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
NAND is NOT of AND gate.
Naveed ABbas said:
9 years ago
If All inputs are high then NAND gate's output will be low.
PA1 said:
10 years ago
It is just simple. The NOT gate can be represented in NAND gate format.
Alizain said:
1 decade ago
Option B is correct.
Izhar khan(jmi) said:
1 decade ago
NAND GATE is a universal gate and behave as a inverter so if input is low then output must be high.
Khushahmaddin said:
1 decade ago
In NAND Gate the frequency is low only when there is high input. But when low or dissimilar frequency input entered the output is high frequency.
i/p1 i/p2 AND NAND
----------------------------
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
NAND is NOT of AND gate.
i/p1 i/p2 AND NAND
----------------------------
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
NAND is NOT of AND gate.
Zakaiter said:
1 decade ago
Because double compliment is always high.
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