Electronics - Logic Gates - Discussion
Discussion Forum : Logic Gates - General Questions (Q.No. 2)
2.
If a signal passing through a gate is inhibited by sending a low into one of the inputs, and the output is HIGH, the gate is a(n):
Discussion:
18 comments Page 1 of 2.
Zakaiter said:
1 decade ago
Because double compliment is always high.
Ashish singhal said:
1 decade ago
NAND GATE=AND+NOT
our output is high when inputs are zero.
Truth Table
A B AB y
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
our output is high when inputs are zero.
Truth Table
A B AB y
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
Ramesh said:
1 decade ago
According NAND gate principle if at lest any one of the input is low the output high.
Sushil said:
1 decade ago
It is only NAND gate in which the output is high when one input is low.
Midhila said:
1 decade ago
Accoring to OR gate if any one i/p is low it will be then high. Why don't you consider that ?
Pallavi said:
1 decade ago
OR gate also satisfy these conditions. So it can also b considered?
Shipra Ghosh said:
1 decade ago
OR gate is also correct.. even i thought it could be the ans. but it isnt.. please justify...
Shawan Banerjee said:
1 decade ago
In NAND Gate the frequency is low only when there is high input. But when low or dissimilar frequency input entered the output is high frequency.
E.Murugan. said:
1 decade ago
OR gate is wrong answer because the signal given in the input is not inhibit in or gate i.e it allows the signal given in the second input terminal.
Example:
A = Input signal which is inhibited.
B = 0 (given in the question).
But in NAND gate, it inhibits the signal and provides high output.
Example:
A = Input signal which is inhibited.
B = 0 (given in the question).
But in NAND gate, it inhibits the signal and provides high output.
Sanjida said:
1 decade ago
i/p1 i/p2 AND NAND
----------------------------
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
NAND is NOT of AND gate.
----------------------------
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
NAND is NOT of AND gate.
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