# Electronics - Logic Gates - Discussion

### Discussion :: Logic Gates - General Questions (Q.No.2)

2.

If a signal passing through a gate is inhibited by sending a low into one of the inputs, and the output is HIGH, the gate is a(n):

 [A]. AND [B]. NAND [C]. NOR [D]. OR

Explanation:

No answer description available for this question.

 Zakaiter said: (Jan 20, 2011) Because double compliment is always high.

 Ashish Singhal said: (Oct 18, 2011) NAND GATE=AND+NOT our output is high when inputs are zero. Truth Table A B AB y 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0

 Ramesh said: (Jan 29, 2012) According NAND gate principle if at lest any one of the input is low the output high.

 Sushil said: (Mar 2, 2012) It is only NAND gate in which the output is high when one input is low.

 Midhila said: (Mar 14, 2012) Accoring to OR gate if any one i/p is low it will be then high. Why don't you consider that ?

 Pallavi said: (Apr 1, 2012) OR gate also satisfy these conditions. So it can also b considered?

 Shipra Ghosh said: (Aug 31, 2012) OR gate is also correct.. even i thought it could be the ans. but it isnt.. please justify...

 Shawan Banerjee said: (Sep 15, 2012) In NAND Gate the frequency is low only when there is high input. But when low or dissimilar frequency input entered the output is high frequency.

 E.Murugan. said: (Nov 28, 2012) OR gate is wrong answer because the signal given in the input is not inhibit in or gate i.e it allows the signal given in the second input terminal. Example: A = Input signal which is inhibited. B = 0 (given in the question). But in NAND gate, it inhibits the signal and provides high output.

 Sanjida said: (Oct 14, 2013) i/p1 i/p2 AND NAND ---------------------------- 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 NAND is NOT of AND gate.

 Khushahmaddin said: (Aug 24, 2014) In NAND Gate the frequency is low only when there is high input. But when low or dissimilar frequency input entered the output is high frequency. i/p1 i/p2 AND NAND ---------------------------- 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 NAND is NOT of AND gate.

 Getaneh Alehegn said: (Dec 12, 2014) Of course, NAND gate also the answer but OR gate also satisfy the conditions. Because OR gate has low output if all inputs are low! x y x+y 0 0 0 0 1 1 1 0 1 1 1 1

 Izhar Khan(Jmi) said: (Dec 17, 2014) NAND GATE is a universal gate and behave as a inverter so if input is low then output must be high.

 Alizain said: (Jul 10, 2015) Option B is correct.

 Pa1 said: (Feb 8, 2016) It is just simple. The NOT gate can be represented in NAND gate format.

 Rita said: (Feb 19, 2016) Its is NAND gate but nt OR gate because: NAND gate. -------------- a b y 0 0 1 <--- 0 1 1. 1 0 1. 1 1 o. OR gate. ----------- a b y. 0 0 0 <--- 0 1 1. 1 0 1. 1 1 1. If you observe both truth table you will get to know. We are sending a low into one of the input and other may be one or zero but the output must be HIGH. It's only in NANA GATE 111.

 Naveed Abbas said: (Feb 14, 2017) If All inputs are high then NAND gate's output will be low.

 Fembright said: (Mar 2, 2017) NOT gate inhibit the action of AND gate, and OR gate is not inhibit by any other gate so B is the answer.