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Electronics and Communication Engineering - Networks Analysis and Synthesis - Discussion

Discussion Forum : Networks Analysis and Synthesis - Section 5 (Q.No. 24)
Networks Analysis and Synthesis
24.
For the circuit shown in the figure, the time constant RC = 1 ms. The input voltage is V1(t) = 2 sin 103 t. The output voltage V0(t) is equal to
sin (103 t - 45°)
sin (103 t + 45°)
sin (103 t - 53°)
sin (103 t + 53°)
Answer: Option
Explanation:

V0(t) = i(t) . jωc

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