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Electronics and Communication Engineering - Digital Electronics - Discussion

Discussion Forum : Digital Electronics - Section 22 (Q.No. 7)
Digital Electronics
7.
In a clocked NAND latch, race condition occur when
R and S are high CLK is low
R and CLK are high and S is low
R, S, CLK are high
R, S, CLK are low
Answer: Option
Explanation:
No answer description is available. Let's discuss.
Discussion:
1 comments Page 1 of 1.
Aman said:   6 years ago
All options are wrong, it is when S AND R are low and the clock is high. Given answer is for NOR LATCH.
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