Electronics and Communication Engineering - Digital Electronics - Discussion


In a clocked NAND latch, race condition occur when

[A]. R and S are high CLK is low
[B]. R and CLK are high and S is low
[C]. R, S, CLK are high
[D]. R, S, CLK are low

Answer: Option C


No answer description available for this question.

Aman said: (Mar 30, 2019)  
All options are wrong, it is when S AND R are low and the clock is high. Given answer is for NOR LATCH.

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