Digital Electronics - Logic Gates - Discussion
Discussion Forum : Logic Gates - General Questions (Q.No. 3)
3.
If a signal passing through a gate is inhibited by sending a LOW into one of the inputs, and the output is HIGH, the gate is a(n):
Discussion:
29 comments Page 2 of 3.
Suhani thakur said:
10 years ago
The simple answer would be to combat the confusion between NAND and OR that whenever there is an i/p signal at 0 the o/p must be 1, whatever be the 2nd i/p.
Krishna said:
1 decade ago
Simply inhibited low signal as a input means one input is fixed that is 0 what ever may be the 2nd input out is constant for that combination i.e. NAND gate check it by drawing NAND gate diagram then it is more clear.
Arun said:
1 decade ago
TAKE THIS IS IN CONSIDERATION.
Here one input is low and another would be high or low. In both cases i.e.either in (0, 1) or in (0, 0) the output should be high. And this condition satisfy by NAND gate.
Here one input is low and another would be high or low. In both cases i.e.either in (0, 1) or in (0, 0) the output should be high. And this condition satisfy by NAND gate.
Kuldeep nagar said:
1 decade ago
But in OR gate if we use 0 and 1 as input then output is also high. Why B is correct answer? D can be answer.
Ankit said:
1 decade ago
NAND - if any one of input is low than output is high.
But.
In OR if both input is low than output is low.
So here only one input is specified which is low, and output is high so NAND gate.
But.
In OR if both input is low than output is low.
So here only one input is specified which is low, and output is high so NAND gate.
P.Narendra kumar said:
1 decade ago
In question he is not discussed about second input .we can take second input as a dont care if we apply the 0&dont care combination NAND gate will give the high output
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Sarvesh said:
1 decade ago
If a signal passing through a gate is inhibited by sending a LOW into one of the inputs, and the output is HIGH, the gate is a(n):
Here already signal is passing through the gate, it is inhibited by applying a low into one of its inputs, that means now the two inputs are low, and the output is high so it may be either NAND or NOR.
Here already signal is passing through the gate, it is inhibited by applying a low into one of its inputs, that means now the two inputs are low, and the output is high so it may be either NAND or NOR.
Shobi said:
1 decade ago
First fix the any one i/p = 0.
Then whatever i/p given to the second pin always lead to high , so
pin1 pin2 o/p(nand)
0 0 1
0 1 1
So even 1 i/p is low o/p will be high in NAND.
Then whatever i/p given to the second pin always lead to high , so
pin1 pin2 o/p(nand)
0 0 1
0 1 1
So even 1 i/p is low o/p will be high in NAND.
Kalai said:
1 decade ago
A B O/P
0 0 1
0 1 1
1 0 1
1 1 0
0 0 1
0 1 1
1 0 1
1 1 0
Madhu Badavath said:
1 decade ago
@Mehak.
IF one the I/P is low,then OR-GATE OUT COMPLETELY DEPENDS ON SECOND I/P only.
1.If second gate I/P is low, then OR-GATE O/P is LOW.
2.If Second gate I/P is HIGH, then OR-GATE O/P is HIGH.
Then our condition won't satisfy.
IF one the I/P is low,then OR-GATE OUT COMPLETELY DEPENDS ON SECOND I/P only.
1.If second gate I/P is low, then OR-GATE O/P is LOW.
2.If Second gate I/P is HIGH, then OR-GATE O/P is HIGH.
Then our condition won't satisfy.
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