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Digital Electronics - Logic Gates

Exercise : Logic Gates - Filling the Blanks
1.

The gates in this figure are implemented using TTL logic. If the input of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.

a steady LOW
a steady HIGH
an undefined level
pulses
Answer: Option
Explanation:
No answer description is available. Let's discuss.
2.

The gates in this figure are implemented using TTL logic. If the output of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.

a steady LOW
a steady HIGH
an undefined level
pulses
Answer: Option
Explanation:
No answer description is available. Let's discuss.
3.
If A is LOW or B is LOW or BOTH are LOW, then X is LOW. If A is HIGH and B is HIGH, then X is HIGH. These rules specify the operation of a(n) ________.
AND gate
OR gate
NAND gate
XOR gate
Answer: Option
Explanation:
No answer description is available. Let's discuss.
4.
A major advantage of ECL logic over TTL and CMOS is ________.
low power dissipation
high speed
both low power dissipation and high speed
neither low power dissipation nor high speed
Answer: Option
Explanation:
No answer description is available. Let's discuss.
5.
The output of an XOR gate is HIGH only when ________.
both inputs = 0
both inputs = 1
the two inputs are unequal
both inputs are undefined
Answer: Option
Explanation:
No answer description is available. Let's discuss.
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